The present invention is directed to logic circuits formed from group III-V semiconductor compounds. In particular, the present invention is directed to integrated logic circuits formed from gallium arsenide (GaAs) field effect transistors (FETs), which include junction field effect transistors (J-FETs) or metal semiconductor field effect transistors (MESFETs).
The need for very high speed analog and digital logic circuits has led to the development of field effect transistors comprised of group III-V compounds, in particular gallium arsenide. In analog circuits, GaAs FETs employed are discrete or integrated components which are used in, for example, analog communications amplifiers. Small signal processing techniques are employed in these analog circuits, and the resultant devices can operate at typically 30 GHz while employing narrow band signals. With respect to digital logic circuits, attempts have been made to manufacture gallium arsenide (GaAs) digital circuits (including GaAs MESFETs, diodes, etc.) on a semi-insulating gallium arsenide wafer. GaAs digital logic circuits operate at a lower frequency than that required for analog logic circuits. Although the frequency employed in GaAs digital logic circuits is approximately one-tenth that of analog circuits, the frequency is nevertheless still very high for digital logic circuits.
GaAs digital logic circuits have been made principally for research purposes and with only limited commercialization due to a variety of technical problems. One of the problems which occurs in the manufacture of GaAs digital logic circuits is that the FETs in the circuit can have relatively large leakage currents from their gates to their source/drain paths. These large leakage currents can increase power dissipation of the logic and degrade the switching characteristics of the circuit. Also, inherent Schottky diodes are formed in GaAs devices, and these inherent Schottky diodes produce currents which are exponential functions of the relative voltages within the circuit. Thus, it is difficult to describe and predict the various voltages and operating characteristics of the circuits. In addition, a uniform ratio of Ga to As is required, but difficult to obtain since the methods for making GaAs substrates and devices have not been perfected and are not highly controllable. Therefore, many design variables and fluctuations in the circuit characteristics occur.
A number of attempts have been made to design and manufacture GaAs digital logic circuits, including integrated circuits (ICs), because they have higher speed due to their intrinsic characteristics of having a higher carrier mobility and lower power requirements. In order to provide GaAs digital logic ICs, the logic circuits developed so far have required relatively complicated circuit structures in order to have consistent operating characteristics within the IC circuit die (i.e., chip) or from die to die.
It should be noted that bipolar and metal oxide semiconductor (MOS) transistors are not typically fabricated from GaAs. That is, GaAs MOS and bipolar transistors are difficult to fabricate. With respect to fabricating MOS devices, a good insulating oxide cannot be formed on the GaAs substrate. With respect to fabricating bipolar devices, it is difficult to form heterojunctions in the GaAs substrate. Although it is possible, it is not commercially feasible. Field effect transistors (FETs) are therefore the most likely candidate for employing GaAs technology. However, unlike silicon FETs, which often isolate the gate from the channel by means of a thermally grown oxide layer, GaAs FETs must be fabricated with a metal gate layer in direct contact with either an epitaxial GaAs layer or an ion-implanted GaAs layer which is defined to include channel regions. Attempts to form insulating layers on the GaAs substrate have proven to be unsuccessful. As a result, the metal gate in the channel region of the FET forms an inherent Schottky diode which, when forward biased, conducts relatively well. The conductive Schottky diode causes many GaAs MESFET logic devices to have undesirable relatively low input impedances.
Various types of GaAs FET logic circuits have been proposed to overcome the above-mentioned problems. However, a number of the proposed circuits require three power supplies and have low integration densities because many circuit components are required in order to produce a desired logic function.
Digital GaAs logic circuits which have been proposed in the prior art belong to one of two categories, depending upon the processing technology used. An example of a logic which is typical of the first category is buffered FET logic (BFL), which employs FET technology and includes only depletion type GaAs circuits which can be manufactured using a simple process and which depend on a single depletion type transistor. The depletion transistors are relatively easy to fabricate and are faster than corresponding silicon devices. Therefore, the first families of GaAs digital logic ICs were made of all depletion type devices. These logic circuits, however, are structurally complex since they require many transistors in order to provide a functioning circuit. The disadvantages of this category of logic circuits are that significant power is dissipated in the circuits, the circuits are structurally complex and a large area is required.
An example of a logic which is typical of the second category of logic circuits is referred to as direct coupled FET logic (DCFL) and is structurally the simplest type of logic within this category. DCFL has a higher integration density and lower power consumption than that of BFL, but it is not as fast as BFL, although it is still faster than silicon devices. A basic DCFL circuit includes a load connected to an enhancement type transistor. The principal drawback to DCFL is its threshold voltage sensitivity. An additional drawback to DCFL is its temperature sensitivity. The temperature sensitivity manifests itself as both a shift in the threshold voltage and an exponential increase in Schottky current. Although the circuit switches properly when operating at room temperature, when operating at a temperature higher than room temperature, the logic circuit may not function. In addition, DCFL degrades with fan-out since when two or more DCFL circuits are connected together, an input Schottky diode at the next stage limits the high logic level and the voltage swing is compressed. Therefore, the greater the number of logic gates connected together, the higher the equivalent load and the greater the limitation of the logic high and the corresponding reduction in logic swing. In summary, DCFL operation starts degrading at temperatures slightly higher than room temperature. Further, when fan-out is increased, the circuit is not commercially feasible for most logic functions.
One approach to overcoming GaAs digital logic IC problems is disclosed in "Analysis of GaAs FETs for Integrated Logic," Lehovec et al., IEEE Transactions on Electron Devices, Volume ED-27, No. 6, June 1980, pp 1074-1091. This publication discloses a GaAs FET circuit in FIG. 19 on page 1085. The input buffer circuit shown in FIG. 19 is a type of DCFL logic and includes a first enhancement FET Q.sub.1 connected in series with a first resistor R1, with the connection point therebetween connected to a gate of a second enhancement type FET Q.sub.2. A second resistor R2 is connected to the drain of the second enhancement type FET Q.sub.2, and a connection node is connected to an output terminal. The use of the fixed resistor R1 is conventional in the art of circuit design and Q.sub.1 and R1 comprise a portion of a source follower circuit. The principal disadvantage of this type of circuit is that resistors are difficult to process and define uniformly in a GaAs manufacturing process, so that non-uniform circuit characteristics are produced. In addition, resistors tend to require either significant layout area or dissipate significant power. Since the number of components which may be fabricated on a die is limited in part by the uniformity of device characteristics, the layout requirements and the thermal dissipation of the components, the circuit in Lehovec et al. appears relatively unsuited for higher levels of integration.
In summary, there is a need in the art for a GaAs digital logic IC having a low power consumption, high integration density, and fast switching speed. There is also a need for such a logic circuit which is easy to manufacture, employs existing process technology, and is compatible with the supply voltages of standard silicon technology, specifically emitter coupled logic (ECL) technology.